## Flat Physical Design
Flat physical design is a bottom-up approach to physical design, based on standard cells, including designing transistors, simulation, setting up a layout, and simulating logic gates.
### Advantages:
- Enables a global view of the chip, allowing designers to see all the cells, facilitating global timing analysis and optimization.
- Time-constrained logic synthesis is relatively easier, and timing violations are more easily resolved.
- For small designs, the computational overhead is relatively small, and the design can be handled and optimized in an intuitive way.
### Disadvantages:
- Requires handling a large amount of computational data, which can consume a significant amount of computational resources.
- Difficult to allocate personnel and resources effectively in large projects, leading to longer design cycles.
- The overall design cycle can be lengthy, impacting the product release time.
- May not be able to fully utilize available resources in large designs, leading to inefficiency.
## Hierarchical Physical Design
Hierarchical physical design breaks down large designs into multiple subdivisions, performing separate layout and routing for each subdivision, and completing the top-level assembly design. This approach focuses on complex modules, shortens the design convergence cycle, and localizes timing problems.
## Silicon Virtual Prototyping
This approach considers dividing the design into sub-divisions at the layout stage and using rapid approximate route planning in the routing stage. During RC extraction, a lumped capacitance model can be used to quickly design convergence evaluation, with a difference of about 5-10% from the final result.
## Summary
- Flat physical design: bottom-up approach, intuitive and accurate but lengthy cycle. Suitable for small-scale designs, achieving global optimization but high resource demand.
- Hierarchical physical design: top-down approach, subdivision of blocks, localization of timing problems. Suitable for large-scale designs, reducing complexity through modularization but limited cross-module optimization.
- Silicon virtual prototyping: rapid, uses experimental routing in routing stage. Used in early design stages, efficient modeling evaluation of physical implementation effects, supports rapid decision-making for complex chips.